1. Field of the Invention
The present invention relates to hybrid circuits and devices fabricated from superconductor materials combined with semiconductor devices that can be operated at low temperatures. More particularly, the present invention relates to a low power, continuous superconductor to semiconductor converter circuit biased for maximum gain but requiring neither a reset circuit nor a clock signal. The present invention is used to convert the small signal levels of superconducting circuits to the much larger signal levels of semiconductor field effect transistor ("FET") devices at very low temperatures, i.e. less than about 30 Kelvin units (K). The operation of FET devices at low temperatures has application for long-wavelength infrared focal plane arrays and hybrid superconductor-semiconductor circuits and systems. This invention also has application for silicon-on-insulator ("SOI") FET devices at higher temperatures.
2. Description of the Related Technology
The discovery of superconductors whose critical operating temperatures are above liquid nitrogen temperature prompted increased interest in hybrid superconducting-semiconducting electronic circuit applications. For signal processing and computer applications the integration of superconducting circuits with semiconductor circuits has been proposed, see U.S. Pat. No. 5,024,993 by Kroger and Ghoshal, and H. Suzuki et al., "A Josephson Driver to Interface Josephson Junctions to Semiconductor Transistors", 1988 IEEE Int. Electron Dev. Meeting Technical Digest, pp. 290-293. There are, however, several problems in interfacing superconducting circuits with semiconductor circuits which interfere with the desired objectives of high-speed, and low-power conversion of superconductor signals to semiconductor signals and vice versa.
At cryo-temperatures (less than about 30K), increased drain-induced barrier lowering and hysteresis effects arising primarily due to carrier freeze-out in the substrate prohibit CMOS devices from being used in sensitive analog circuits. These effects are also well-known but no effective solution has been offered to date. The non-ideal characteristics of CMOS at lower temperatures are described in the following papers (M. Aoki, S. Hanamura, T. Masuhara and K. Yano, "Performance and Hot Carrier Effects of Small Cryo-CMOS Devices", IEEE Transactions on Electron Devices, vol. 34, pp. 8-18, January 1987; E. Simoen, B. Dierickx, L. Warmerdam, J. Vermeiren and C. Claeys, "Freeze-out Effects on NMOS Transistor Characteristics at 4K", IEEE Transactions on Electron Devices, vol. 36, pp. 1155-1161, June 1989; L. Deferm, E. Simoen and C. Claeys, "The Importance of the Internal Bulk-Source Potential on the Low Temperature Kink in NMOSTs", IEEE Transactions on Electron Devices, vol. 38, pp. 1459-1466, June 1991; T. Elewa, F. Balestra, S. Cristoloveanu, I. Hafez, J-P. Colinge, A-J. Auberton-Herve and J. Davis, "Performance and Physical Mechanisms in SIMOX MOS Transistors Operated at Very Low Temperatures", IEEE Transactions on Electron Devices, vol. 37, pp. 1007-1019, April 1990).
Some of the problems associated with carrier freeze-out in the substrate can be reduced by fabricating CMOS devices on thin epitaxial layers grown on degenerately doped substrates (see for example, S. Broadbent, "Operation of CMOS Devices at 10K", Proceedings of the Symposium on Low Temperature Electronics, vol. 88-9, The Electrochemical Society, pp. 170-176, October 1987). In some cases, the retrograded wells are used. In addition to doping the substrate, the substrate needs to be biased such that the substrate-to-source junctions of the NMOS transistors are reverse biased. This method is complex and does not completely eliminate the hysteresis at low drain currents, thereby making it unsuitable for sensitive analog operation. When the epitaxial layer is thin (.about.10 .mu.m), the boron out-diffusion from the degenerately doped substrate increases the acceptor concentration through most of the epitaxial layer. This spoils the threshold voltage of the NMOS transistors and makes the transistors susceptible to latch-up at higher temperatures. Thus the circuits cannot be tested at room temperature. When the epitaxial layers are thick (.about.20 .mu.m), this method cannot eliminate the hysteresis and is largely ineffective. The method also increases the threshold voltages of the NMOS transistors, although the effect has not been explored in detail in the prior art. This method is also not applicable for short-channel devices, since the heavily doped substrate is relatively far from the channel.
A recommended practice for operation of CMOS devices at low temperatures is to provide a grounded bulk contact ring (or channel contact in the case of SOI devices) around every device and prevent the bulk region near the devices from floating at arbitrary potential. This can reduce time-dependent fluctuations of the threshold voltages and make the devices suitable for some digital applications (O. Kindl, W. Langheinrich, G. Fischer, "Cryo-CMOS Technology", Proceedings of the Symposium on Low Temperature Electronics, vol. 88-9, The Electrochemical Society, pp. 518-523, October 1987; J. Wang, N. Kistler, J. Woo and C. Viswanathan, "Threshold Instability at Low Temperatures in Partially Depleted Thin-Film SOI MOSFETs", IEEE Electron Device Letters, vol. 12, pp. 300-302, June 1991).
If symmetrical PMOS and NMOS devices with the same threshold voltages are required, a common practice is to use p+ polysilicon gates for PMOS transistors and n+ polysilicon gates for NMOS transistors. This "dual-poly" process was first used by researchers at IBM for their 77 K optimized CMOS devices (J. Y. Sun, Y. Taur, R. Dennard and S. Klepner, "Submicrometer-Channel CMOS for Low Temperature Operation", IEEE Transactions on Electron Devices, vol. 34, pp. 19-27, January 1987) and later by researchers at Technical University of Darmstadt (O. Kindl, W. Langheinrich, G. Fischer, "Cryo-CMOS Technology", Proceedings of the Symposium on Low Temperature Electronics, vol. 88-9, The Electrochemical Society, pp. 518-523, October 1987) for their 2-4K cryo-CMOS devices.
Superconducting circuit technology utilizes signal voltage levels approximately 500 times smaller than, and incompatible with, the signal voltage levels of semiconductor logic circuit technology. Both of the signal current levels, however, are comparable. These signal current levels are typically 0.1 to 30 milliamperes. The superconductor signal voltage level is typically 2 millivolts and may be up to 150 millivolts when utilizing special output driver circuits. Semiconductor logic signal voltage levels have been for the last ten years, 5 volts for complementary metal oxide semiconductor ("CMOS") and 1 volt for emitter coupled logic ("ECL"); however, improvements in these technologies have resulted in new designs requiring only 3 volts for CMOS and 400 millivolts for ECL.
Converting from semiconductor signal voltage levels to superconducting signal voltage levels is easily done with attenuators. Converting from superconducting signals to semiconductor signals, however, requires high gain voltage amplifiers to increase the millivolt signal levels of the superconductor signals to compatible semiconductor signal levels. High gain voltage amplifiers are difficult to implement using superconductor technology; therefore, semiconductor technology must be utilized to achieve the required voltage gain.
Converting the 2 millivolt superconductor circuit signal to a compatible voltage level of 3 or 5 volts for CMOS requires amplification of over 500 times the input signal level. This magnitude of amplification may be obtained by use of high gain voltage amplifiers. In designing high gain voltage amplifiers, however, there is great difficulty in simultaneously achieving high gain, wide bandwidth, short signal delay, low power, small size, high power supply noise rejection ratio, low noise, and insensitivity to temperature variation.
To minimize signal delay and stray noise pickup, it is desirable to place the circuitry of both the superconductors and semiconductors closely together. Minimizing the superconductor and semiconductor device sizes and spacing therebetween achieves the most desirable results as to speed of operation and signal noise immunity. Superconductor circuits must operate in cryo-temperatures. Cryo-temperatures, however, greatly affect semiconductor device operating parameters such as gain-bandwidth-delay, power dissipation versus drive capability, freedom from oscillation, bias stability, and rejection of noise and other error sources. As an example, a transistor has hysteresis at cryo-temperatures. This hysteresis may be the source of very large signal error.
In a high gain semiconductor amplifier circuit a small amount of transistor hysteresis will be amplified to a large output error. In similar fashion, bias circuit instability may induce noise and other errors. Therefore, high gain amplifiers for both analog and digital signals require precise and stable biasing; for an amplifier gain of 500 the bias stability must be controlled to less than one millivolt.
In digital circuits, most of the noise introduced is from switching noise on the semiconductor device power source. Therefore, amplifiers for digital circuits must have very good power supply noise rejection ratio ("PSRR"). For an amplifier circuit to operate in a cryo-environment, it should dissipate minimal power in the form of heat, where 100 microwatts per amplifier circuit is considered large and 1 microwatt small.
A binary digital signal consists of two states or voltage levels. A logic "1" or high state may be represented by a positive voltage greater than the voltage level of a logic "0" or low state. The low state voltage level may be slightly positive, at ground or even negative. A converter is a combination of an amplifier and any additional devices necessary to maintain output voltage levels with margins for input noise. Noise margins are-affected by device fabrication parameters.
An example of a converter circuit to convert superconductor signals to semiconductor signals is illustrated in U.S. Pat. No. 5,024,993 entitled "Superconducting-Semiconducting Circuits, Devices and Systems" by Kroger and Ghoshal. The Kroger and Ghoshal patent teaches that the amplifying FET is switched across its turn-on threshold, the use of highly asymmetric transistor sizes having large transistor areas with non-minimum capacitance nodes, and the requirement of a clock input to its biasing circuit which is used to reset the amplifier after converting each bit of data at high data rates.
There is a need for a superconductor to semiconductor converter circuit having low power dissipation, low capacitance, good power supply noise rejection, bias point stability for maximum gain, and requiring no external reset circuitry. It therefore is an object of the present invention to convert superconductor signal levels to semiconductor signal levels with circuits having low power dissipation, low capacitance for high speed, good power supply noise rejection, optimal biasing for maximum amplifier stage gain and requiring no external logic reset circuits.
Another object of the present invention is to amplify millivolt signal levels to multivolt signal levels.
Yet another object of the present invention is to convert millivolt signals to multivolt signals while operating at cryogenic temperatures.
Another object of the present invention is to amplify small signal levels from MOS memory bit lines to semiconductor signal voltage levels.
Yet a further object of the present invention is to amplify millivolt analog signals.
A further object of the present invention is to substantially eliminate the hysteresis problem in CMOS operating at cryogenic temperatures for both digital and analog applications.